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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. iso1042 sllsf09c ? december 2017 ? revised september 2018 iso1042 isolated can transceiver with 70-v bus fault protection and flexible data rate 1 1 features 1 ? meets the iso 11898-2:2016 and iso 11898- 5:2007 physical layer standards ? supports classic can up to 1 mbps and fd (flexible data rate) up to 5 mbps ? low loop delay: 152 ns ? protection features ? dc bus fault protection voltage: 70 v ? hbm esd tolerance on bus pins: 16 kv ? driver dominant time out (txd dto) ? undervoltage protection on v cc1 and v cc2 ? common-mode voltage range: 30 v ? ideal passive, high impedance bus terminals when unpowered ? high cmti: 100 kv/ s ? v cc1 voltage range: 1.71 v to 5.5 v ? supports 1.8-v, 2.5-v, 3.3-v and 5.0-v logic interface to the can controller ? v cc2 voltage range: 4.5 v to 5.5 v ? robust electromagnetic compatibility (emc) ? system-level esd, eft, and surge immunity ? low emissions ? ambient temperature range: ? 40 c to +125 c ? 16-soic and 8-soic package options ? safety-related certifications: ? 7071-v pk v iotm and 1500-v pk v iorm (reinforced and basic options) per din v vde v 0884-11 ? 5000-v rms isolation for 1 minute per ul 1577 ? iec 60950-1, iec 60601-1 and en 61010-1 certifications ? cqc, tuv and csa certifications ? all certifications planned 2 applications ? ac and servo drives ? solar inverters ? plc and dcs communication modules ? elevators and escalators ? industrial power supplies ? battery charging and management 3 description the iso1042 device is a galvanically-isolated controller area network (can) transceiver that meets the specifications of the iso11898-2 (2016) standard. the iso1042 device offers 70-v dc bus fault protection and 30-v common-mode voltage range. the device supports up to 5-mbps data rate in can fd mode allowing much faster transfer of payload compared to classic can. this device uses a silicon dioxide (sio 2 ) insulation barrier with a withstand voltage of 5000 v rms and a working voltage of 1060 v rms . electromagnetic compatibility has been significantly enhanced to enable system-level esd, eft, surge, and emissions compliance. used in conjunction with isolated power supplies, the device protects against high voltage, and prevents noise currents from the bus from entering the local ground. the iso1042 device is available for both basic and reinforced isolation (see reinforced and basic isolation options ). the iso1042 device supports a wide ambient temperature range of ? 40 c to +125 c. the device is available in the soic-16 (dw) package and a smaller soic-8 (dwv) package. device information (1) part number package body size (nom) iso1042 soic (8) 5.85 mm 7.50 mm soic (16) 10.30 mm 7.50 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. reinforced and basic isolation options feature iso1042x iso1042bx protection level reinforced basic surge test voltage 10000 v pk 6000 v pk isolation rating 5000 v rms 5000 v rms working voltage 1060 v rms / 1500 v pk 1060 v rms / 1500 v pk application diagram productfolder 12 4 3 76 5 txd v cc1 rxd gnd1 canh canl 8 v cc2 mcu rxd txd v dd dgnd digital ground iso ground can bus galvanic isolation barrier iso1042 gnd2 v cc1 v cc2 copyright ? 2017, texas instruments incorporated support &community tools & software technical documents ordernow
2 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 transient immunity .................................................... 5 6.4 recommended operating conditions ....................... 5 6.5 thermal information .................................................. 6 6.6 power ratings ........................................................... 6 6.7 insulation specifications ............................................ 7 6.8 safety-related certifications ..................................... 8 6.9 safety limiting values .............................................. 8 6.10 electrical characteristics - dc specification ........... 9 6.11 switching characteristics ...................................... 11 6.12 insulation characteristics curves ......................... 12 6.13 typical characteristics .......................................... 13 7 parameter measurement information ................ 15 7.1 test circuits ............................................................ 15 8 detailed description ............................................ 19 8.1 overview ................................................................. 19 8.2 functional block diagram ....................................... 19 8.3 feature description ................................................. 19 8.4 device functional modes ........................................ 23 9 application and implementation ........................ 24 9.1 application information ............................................ 24 9.2 typical application .................................................. 24 9.3 devicenet application ............................................. 27 10 power supply recommendations ..................... 28 11 layout ................................................................... 29 11.1 layout guidelines ................................................. 29 11.2 layout example .................................................... 29 12 device and documentation support ................. 31 12.1 documentation support ........................................ 31 12.2 receiving notification of documentation updates 31 12.3 community resource ............................................ 31 12.4 trademarks ........................................................... 31 12.5 electrostatic discharge caution ............................ 31 12.6 glossary ................................................................ 31 13 mechanical, packaging, and orderable information ........................................................... 31 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision b (july 2018) to revision c page ? initial release ........................................................................................................................................................................ 1 changes from revision a (may 2018) to revision b page ? increased the size of the gnd2 plane and changed the nc pin to gnd2 in the 16-dw layout example ......................... 30 changes from original (december 2017) to revision a page ? changed pin 10 from nc to gnd2 ......................................................................................................................................... 3
3 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 5 pin configuration and functions dw package 16-pin soic top view pin functions ? 16 pins pin i/o description no. name 1 v cc1 ? digital-side supply voltage, side 1 2 gnd1 ? digital-side ground connection, side 1 3 txd i can transmit data input (low for dominant and high for recessive bus states) 4 nc ? not connected 5 rxd o can receive data output (low for dominant and high for recessive bus states) 6 nc ? not connected 7 nc ? not connected 8 gnd1 ? digital-side ground connection, side 1 9 gnd2 ? transceiver-side ground connection, side 2 10 11 v cc2 ? transceiver-side supply voltage, side 2. must be externally connected to pin 16. 12 canl i/o low-level can bus line 13 canh i/o high-level can bus line 14 nc ? not connected 15 gnd2 ? transceiver-side ground connection, side 2 16 v cc2 ? transceiver-side supply voltage, side 2. must be externally connected to pin 11. 1 v cc1 16 v cc2 2 gnd1 15 gnd2 3 txd 14 nc 4 nc 13 canh 5 rxd 12 canl 6 nc 11 v cc2 7 nc 10 gnd2 8 gnd1 9 gnd2 isolation not to scale
4 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated dwv package 8-pin soic top view pin functions ? 8 pins pin i/o description no. name 1 v cc1 ? digital-side supply voltage, side 1 2 txd i can transmit data input (low for dominant and high for recessive bus states) 3 rxd o can receive data output (low for dominant and high for recessive bus states) 4 gnd1 ? digital-side ground connection, side 1 5 gnd2 ? transceiver-side ground connection, side 2 6 canl i/o low-level can bus line 7 canh i/o high-level can bus line 8 v cc2 ? transceiver-side supply voltage, side 2 1 v cc1 8 v cc2 2 txd 7 canh 3 rxd 6 canl 4 gnd1 5 gnd2 not to scale isolation
5 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values except differential i/o bus voltages are with respect to the local ground terminal (gnd1 or gnd2) and are peak voltage values. (3) maximum voltage must not exceed 6 v 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit v cc1 supply voltage, side 1 -0.5 6 v v cc2 supply voltage, side 2 -0.5 6 v v io logic input and output voltage range (txd and rxd) -0.5 v cc1 +0.5 (3) v i o output current on rxd pin -15 15 ma v bus voltage on bus pins (canh, canl) -70 70 v v bus_diff differential voltage on bus pins (canh-canl) -70 70 v t j junction temperature -40 150 t stg storage temperature -65 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 all pins (1) 6000 v canh and canl to gnd2 (1) 16000 v electrostatic discharge charged device model (cdm), per jedec specification jesd22-c101 all pins (2) 1500 6.3 transient immunity parameter test conditions value unit v pulse iso7637-2 transients according to gift - ict can emc test specification pulse 1; can bus terminals (canh, canl) to gnd2 -100 v pulse 2; can bus terminals (canh, canl) to gnd2 75 v pulse 3a; can bus terminals (canh, canl) to gnd2 -150 v pulse 3b; can bus terminals (canh, canl) to gnd2 100 v 6.4 recommended operating conditions min max unit v cc1 supply voltage, side 1, 1.8-v operation 1.71 1.89 v supply voltage, side 1, 2.5-v, 3.3-v and 5.5-v operation 2.25 5.5 v v cc2 supply voltage, side 2 4.5 5.5 v t a operating ambient temperature -40 125 c
6 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.5 thermal information thermal metric (1) iso1042 unit dw (soic) dwv (soic) 16 pins 8 pins r ja junction-to-ambient thermal resistance 69.9 100 c/w r jc(top) junction-to-case (top) thermal resistance 31.8 40.8 c/w r jb junction-to-board thermal resistance 29.0 51.8 c/w jt junction-to-top characterization parameter 13.2 16.8 c/w jb junction-to-board characterization parameter 28.6 49.8 c/w r jc(bot) junction-to-case (bottom) thermal resistance - - c/w 6.6 power ratings parameter test conditions min typ max unit p d maximum power dissipation (both sides) v cc1 = v cc2 = 5.5 v, t j = 150 c, r l = 50 ? , a repetitive pattern on txd with 1 ms time period, 990 s low time, and 10 s high time. 385 mw p d1 maximum power dissipation (side-1) v cc1 = v cc2 = 5.5 v, t j = 150 c, r l = 50 ? , input a 2-v pk-pk 2.5-mhz 50% duty cycle differential square wave on canh-canl 25 mw p d2 maximum power dissipation (side-2) v cc1 = v cc2 = 5.5 v, t j = 150 c, r l = 50 ? , a repetitive pattern on txd with 1 ms time period, 990 s low time, and 10 s high time. 360 mw
7 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. (2) iso1042 is suitable for safe electrical insulation and iso1042b is suitable for basic electrical insulation only within the safety ratings. compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (4) apparent charge is electrical discharge caused by a partial discharge (pd). (5) all pins on each side of the barrier tied together creating a two-pin device. 6.7 insulation specifications parameter test conditions specifications unit dw-16 dwv-8 iec 60664-1 clr external clearance (1) side 1 to side 2 distance through air > 8 > 8.5 mm cpg external creepage (1) side 1 to side 2 distance across package surface > 8 > 8.5 mm dti distance through the insulation minimum internal gap (internal clearance) > 17 > 17 m cti comparative tracking index iec 60112; ul 746a > 600 > 600 v material group according to iec 60664-1 i i overvoltage category rated mains voltage 600 v rms i-iv i-iv rated mains voltage 1000 v rms i-iii i-iii din v vde v 0884-11:2017-01 (2) v iorm maximum repetitive peak isolation voltage ac voltage (bipolar) 1500 1500 v pk v iowm maximum isolation working voltage ac voltage (sine wave); time-dependent dielectric breakdown (tddb) test; 1060 1060 v rms dc voltage 1500 1500 v dc v iotm maximum transient isolation voltage v test = v iotm , t = 60 s (qualification); v test = 1.2 v iotm , t = 1 s (100% production) 7071 7071 v pk v iosm maximum surge isolation voltage iso1042 (3) test method per iec 62368-1, 1.2/50 s waveform, v test = 1.6 v iosm = 10000 v pk (qualification) 6250 6250 v pk maximum surge isolation voltage iso1042b (3) test method per iec 62368-1, 1.2/50 s waveform, v test = 1.3 v iosm = 6000 v pk (qualification) 4615 4615 v pk q pd apparent charge (4) method a: after i/o safety test subgroup 2/3, v ini = v iotm , t ini = 60 s; v pd(m) = 1.2 v iorm , t m = 10 s 5 5 pc method a: after environmental tests subgroup 1, v ini = v iotm , t ini = 60 s; iso1042: v pd(m) = 1.6 v iorm , t m = 10 s iso1042b: v pd(m) = 1.2 v iorm , t m = 10 s 5 5 method b1: at routine test (100% production) and preconditioning (type test), v ini = v iotm , t ini = 1 s; iso1042: v pd(m) = 1.875 v iorm , t m = 1 s iso1042b: v pd(m) = 1.5 v iorm , t m = 1 s 5 5 c io barrier capacitance, input to output (5) v io = 0.4 sin (2 ft), f = 1 mhz 1 1 pf r io insulation resistance, input to output (5) v io = 500 v, t a = 25 c > 10 12 > 10 12 v io = 500 v, 100 c t a 150 c > 10 11 > 10 11 v io = 500 v at t s = 150 c > 10 9 > 10 9 pollution degree 2 2 climatic category 40/125/ 21 40/125/ 21 ul 1577 v iso withstand isolation voltage v test = v iso , t = 60 s (qualification); v test = 1.2 v iso , t = 1 s (100% production) 5000 5000 v rms
8 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.8 safety-related certifications vde csa ul cqc tuv plan to certify according to din v vde v 0884- 11:2017- 01 plan to certify according to iec 60950-1, iec 62368-1 and iec 60601-1 plan to certify according to ul 1577 component recognition program plan to certify according to gb4943.1-2011 plan to certify according to en 61010-1:2010 (3rd ed) and en 60950- 1:2006/a11:2009/a1:2010 /a12:2011/a2:2013 maximum transient isolation voltage, 7071 v pk ; maximum repetitive peak isolation voltage, 1500 v pk ; maximum surge isolation voltage, iso1042: 6250 v pk (reinforced) iso1042b: 4615 v pk (basic) csa 60950-1-07+a1+a2 and iec 60950-1 2nd ed., for pollution degree 2, material group i iso1042: 800 v rms reinforced isolation iso1042b: 800 v rms basic isolation ---------------- csa 60601- 1:14 and iec 60601-1 ed. 3.1, iso1042: 2 mopp (means of patient protection) 250 v rms (354 v pk ) maximum working voltage single protection, 5000 v rms reinforced insulation, altitude 5000 m, tropical climate, 700 v rms maximum working voltage en 61010-1:2010 (3rd ed) iso1042: 600 v rms reinforced isolation iso1042b: 600 v rms basic isolation ---------------- en 60950- 1:2006/a11:2009/a1:2010 /a12:2011/a2:2013 iso1042: 800 v rms reinforced isolation iso1042b: 800 v rms basic isolation certificate planned certificate planned certificate planned certificate planned certificate planned (1) the maximum safety temperature, t s , has the same value as the maximum junction temperature, t j , specified for the device. the i s and p s parameters represent the safety current and safety power respectively. the maximum limits of i s and p s should not be exceeded. these limits vary with the ambient temperature, t a . the junction-to-air thermal resistance, r ja , in the table is that of a device installed on a high-k test board for leaded surface-mount packages. use these equations to calculate the value for each parameter: t j = t a + r ja p, where p is the power dissipated in the device. t j(max) = t s = t a + r ja p s , where t j(max) is the maximum allowed junction temperature. p s = i s v i , where v i is the maximum input voltage. 6.9 safety limiting values safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. parameter test conditions min typ max unit dw-16 package i s safety input, output, or supply current r ja = 69.9 c/w, v i = 5.5 v, t j = 150 c, t a = 25 c, see figure 1 325 ma r ja = 69.9 c/w, v i = 3.6 v, t j = 150 c, t a = 25 c, see figure 1 496 r ja = 69.9 c/w, v i = 2.75 v, t j = 150 c, t a = 25 c, see figure 1 650 r ja = 69.9 c/w, v i = 1.89 v, t j = 150 c, t a = 25 c, see figure 1 946 p s safety input, output, or total power r ja = 69.9 c/w, t j = 150 c, t a = 25 c, see figure 3 1788 mw t s maximum safety temperature 150 c dwv-8 package i s safety input, output, or supply current r ja = 100 c/w, v i = 5.5 v, t j = 150 c, t a = 25 c, see figure 2 227 ma r ja = 100 c/w, v i = 3.6 v, t j = 150 c, t a = 25 c, see figure 2 347 r ja = 100 c/w, v i = 2.75 v, t j = 150 c, t a = 25 c, see figure 2 454 r ja = 100 c/w, v i = 1.89 v, t j = 150 c, t a = 25 c, see figure 2 661 p s safety input, output, or total power r ja = 100 c/w, t j = 150 c, t a = 25 c, see figure 4 1250 mw t s maximum safety temperature 150 c
9 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.10 electrical characteristics - dc specification over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit supply characteristics i cc1 supply current side 1 v cc1 =1.71 v to 1.89 v, txd = 0 v, bus dominant 2.3 3.5 ma v cc1 = 2.25 v to 5.5 v, txd = 0 v, bus dominant 2.4 3.5 ma v cc1 = 1.71 v to 1.89 v, txd = v cc1 , bus recessive 1.2 2.1 ma v cc1 = 2.25 v to 5.5 v, txd = v cc1 , bus recessive 1.3 2.1 ma i cc2 supply current side 2 txd = 0 v, bus dominant, r l = 60 43 73.4 ma txd = v cc1 , bus recessive, r l = 60 2.8 4.1 ma uv vcc1 rising under voltage detection, side 1 1.7 v uv vcc1 falling under voltage detection, side 1 1.0 v v hys(uvc c1) hysterisis voltage on v cc1 undervoltage lock-out 75 125 mv uv vcc2 rising under voltage detection, side 2 4.2 4.45 v uv vcc2 falling under voltage detection, side 2 3.8 4.0 4.25 v v hys(uvc c2) hysterisis voltage on v cc2 undervoltage lock-out 200 mv txd terminal v ih high level input voltage 0.7 v cc1 v v il low level input voltage 0.3 v cc1 v i ih high level input leakage current txd = v cc1 1 ua i il low level input leakage current txd = 0v -20 ua c i input capacitance vin = 0.4 x sin(2 x x 1e+6 x t) + 2.5 v, v cc1 = 5 v 3 pf rxd terminal v oh - v cc1 high level output voltage see figure 18 , i o = -4 ma for 4.5 v v cc1 5.5 v -0.4 -0.2 v see figure 18 , i o = -2 ma for 3.0 v v cc1 3.6 v -0.2 -0.07 v see figure 18 , i o = -1 ma for 2.25 v v cc1 2.75 v -0.1 -0.04 v see figure 18 , i o = -1 ma for 1.71 v v cc1 1.89 v -0.1 -0.045 v v ol low level output voltage see figure 18 , i o = 4 ma for 4.5 v v cc1 5.5 v 0.2 0.4 v see figure 18 , i o = 2 ma for 3.0 v v cc1 3.6 v 0.07 0.2 v see figure 18 , i o = 1 ma for 2.25 v v cc1 2.75 v 0.035 0.1 v see figure 18 , i o = 1 ma for 1.71 v v cc1 1.89 v 0.04 0.1 v driver electrical characteristics v o(dom) bus output voltage(dominant), canh see figure 15 and figure 16 , txd = 0 v, 50 r l 65 , and c l = open 2.75 4.5 v bus output voltage(dominant), canl see figure 15 and figure 16 , txd = 0 v, 50 r l 65 , and c l = open 0.5 2.25 v v o(rec) bus output voltage(recessive), canh and canl see figure 15 and figure 16 , txd = v cc1 and r l = open 2.0 0.5 x vcc2 3.0 v
10 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics - dc specification (continued) over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v od(dom) differential output voltage(dominant) see figure 15 and figure 16 , txd = 0 v, 45 < r l < 50 , and c l = open 1.4 3.0 v differential output voltage(dominant) see figure 15 and figure 16 , txd = 0 v, 50 < r l < 65 , and c l = open 1.5 3.0 v differential output voltage(dominant) see figure 15 and figure 16 , txd = 0 v, rl = 2240 , and c l = open 1.5 5.0 v v od(rec) differential output voltage(recessive) see figure 15 and figure 16 , txd = v cc1 , rl = 60 , and c l = open -120.0 12.0 mv differential output voltage(recessive) see figure 15 and figure 16 , txd = v cc1 , r l = open, and c l = open -50.0 50.0 mv v sym_dc output symmetry (v cc2 - v o(canh) - v o(canl) ) see figure 15 and figure 16 , r l = 60 and c l = open, txd = v cc1 or 0 v -400.0 400.0 mv i so(ss_do m) short circuit current steady state output current, dominant see figure 23 , vcanh = -5v, canl = open, and txd = 0v -100.0 ma see figure 23 , vcanl = 40v, canh = open, and txd = 0v 100.0 ma i so(ss_re c) short circuit current steady state output current, recessive see figure 23 , -27 < vbus < 32v, vbus = canh = canl, and txd = v cc1 -5.0 5.0 ma receiver electrical characteristics v it differential input threshold voltage see figure 18 and table 1 , |vcm| < = 20v 500.0 900.0 mv differential input threshold voltage see figure 18 and table 1 , 20 < = |vcm| < = 30v 400.0 1000.0 v hys hysteresis voltage for differential input threshold see figure 18 and table 1 120 v cm input common mode range see figure 18 and table 1 -30.0 30.0 v i off(lkg) power-off bus input leakage current canh = canl = 5v, vcc to gnd via 0 and 47k resistor 4.8 ua c i input capacitance to ground txd = v cc1 24.0 30 pf c id differential input capacitance txd = v cc1 12.0 15 pf r id differential input resistance txd = v cc1 ; -30 v vcm +30 v 30.0 80.0 k r in input resistance (canh or canl) txd = v cc1 ; -30 v vcm +30 v 15.0 40.0 k r in(m) input resistance matching: (1 - r in(canh) /r in(canl) ) x 100% v canh = v canl = 5 v -2.0 2.0 % thermal shutdown t tsd thermal shutdown temperature 170 t tsd_hys t thermal shutdown hysteresis 5
11 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.11 switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit device switching characteristics t prop(lo op1) total loop delay, driver input txd to receiver rxd, recessive to dominant see figure 20 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns; 1.71 v < v cc1 < 1.89 v 70 125 198.0 ns see figure 20 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns; 2.25 v < v cc1 < 5.5 v 70 122 192.0 ns t prop(lo op2) total loop delay, driver input txd to receiver rxd, dominant to recessive see figure 20 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns; 1.71 v < v cc1 < 1.89 v 70 155 215.0 ns see figure 20 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns; 2.25 < v cc1 < 5.5 v 70 152 215.0 ns t uv_re_e nable re-enable time after undervoltage event time for device to return to normal operation from vcc1 or vcc2 under voltage event 300.0 s cmti common mode transient immunity v cm = 1200 v pk , see figure 24 85 100 kv/ s driver switching characteristics t phr propagation delay time, high txd to driver recessive see figure 17 , r l = 60 and c l = 100 pf; input rise/fall time (10% to 90%) on txd =1 ns 76 120 ns t pld propagation delay time, low txd to driver dominant 61 120 t sk(p) pulse skew (|tphr - tpld|) 14 t r differential output signal rise time 45 t f differential output signal fall time 45 t txd_dto dominant time out see figure 22 , r l = 60 and c l = open 1.2 3.8 ms receiver switching characteristics t prh propagation delay time, bus recessive input to rxd high output see figure 19 , c l(rxd) = 15 pf 75 130 ns t pdl propogation delay time, bus dominant input to rxd low output 63 130 ns t r output signal rise time(rxd) 1.4 ns t f output signal fall time(rxd) 1.8 ns fd timing parameters t bit(bus) bit time on can bus output pins with t bit(txd) = 500 ns see figure 21 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns 435.0 530.0 ns bit time on can bus output pins with t bit(txd) = 200 ns see figure 21 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns 155.0 210.0 ns t bit(rxd) bit time on rxd bus output pins with t bit(txd) = 500 ns see figure 21 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns 400 550.0 ns bit time on rxd bus output pins with t bit(txd) = 200 ns see figure 21 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns 120.0 220.0 ns
12 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated switching characteristics (continued) over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit ? trec receiver timing symmetry with t bit(txd) = 500 ns see figure 21 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns; trec = t bit(rxd) - t bit(bus) -65.0 40.0 ns receiver timing symmetry with t bit(txd) = 200 ns see figure 21 , r l = 60 ? , c l = 100 pf, c l(rxd) = 15 pf; input rise/fall time (10% to 90%) on txd =1 ns; trec = t bit(rxd) - t bit(bus) -45.0 15.0 ns 6.12 insulation characteristics curves figure 1. thermal derating curve for limiting current per vde for dw-16 package figure 2. thermal derating curve for limiting current per vde for dwv-8 package figure 3. thermal derating curve for limiting power per vde for dw-16 package figure 4. thermal derating curve for limiting power per vde for dwv-8 package ambient temperature ( q c) safety limiting current (ma) 0 50 100 150 200 0 100 200 300 400 500 600 700 800 900 1000 d003 v cc1 =1.89 v v cc1 = 2.75 v v cc1 = 3.6 v v cc1 = v cc2 = 5.5 v ambient temperature ( q c) safety limiting current (ma) 0 50 100 150 200 0 100 200 300 400 500 600 700 d001 v cc1 = 1.89 v v cc1 = 2.75 v v cc1 = 3.6 v v cc1 = v cc2 = 5.5 v ambient temperature ( q c) safety limiting power (mw) 0 50 100 150 200 0 200 400 600 800 1000 1200 1400 d002 ambient temperature ( q c) safety limiting power (mw) 0 50 100 150 200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 d004
13 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.13 typical characteristics v cc1 = 5 v r l = 60 c l(rxd) = 15 pf temp = 25 c figure 5. i cc2 vs v cc2 for recessive, dominant and different can datarates v cc2 = 5 v r l = 60 c l(rxd) = 15 pf temp = 25 c figure 6. i cc1 vs datarate v cc1 = v cc2 = 5 v r l = 60 c l(rxd) = 15 pf figure 7. i cc2 vs ambient temperature for recessive, dominant and different can datarates v cc1 = v cc2 = 5 v r l = 60 c l(rxd) = 15 pf temp = 25 c figure 8. : icc1 vs ambient temperature for recessive, dominant and different can datarates. v cc1 = v cc2 = 5 v r l = 60 c l(rxd) = 15 pf figure 9. loop delay vs ambient temperature v cc = 5 v v cc1 = 5 v r l = 60 c l = open figure 10. v od(dom) over temperature temperature ( q c) i cc2 (ma) -60 -40 -20 0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 40 45 d003 recessive dominant 500 kbps 1 mbps 2 mbps 5 mbps temperature ( q c) i cc1 (ma) -60 -40 -20 0 20 40 60 80 100 120 140 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 d004 recessive dominant 500 kbps 1 mbps 2 mbps 5 mbps temperature (c) v od(dom) (v) -55 -35 -15 5 25 45 65 85 105 125 0 0.5 1 1.5 2 2.5 3 d001 temperature ( q c) loop delay (ns) -60 -40 -20 0 20 40 60 80 100 120 140 100 110 120 130 140 150 160 170 180 d005d005 t prop(loop1) t prop(loop2) data rate (mbps) i cc1 (ma) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2 2.25 2.3 d002 v cc1 =1.71 v v cc1 =1.8 v v cc1 =2.5 v v cc1 =3.3 v v cc1 =5 v v cc1 =5.5 v v cc2 (v) i cc2 (ma) 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 0 5 10 15 20 25 30 35 40 45 50 d001 recessive dominant 500 kbps 1 mbps 2 mbps 5 mbps
14 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) v cc1 = 5 v r l = 60 c l = open temp = 25 c figure 11. v od(dom) over v cc v cc1 = v cc2 = 5 v r l = 60 c l = 100 pf c l(rxd) = 15 pf figure 12. typical txd, rxd, canh and canl waveforms at 1 mbps txd = v cc1 r l = 60 v cc1 = v cc2 = 5 v figure 13. glitch free power up on v cc1 ? can bus remains recessive txd = v cc1 r l = 60 v cc1 = v cc2 = 5 v figure 14. glitch free power up on v cc2 ? can bus remains recessive v cc (v) v od(dom) (v) 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 0 0.5 1 1.5 2 2.5 3 d002
15 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 7 parameter measurement information 7.1 test circuits figure 15. driver voltage, current and test definitions figure 16. bus logic state voltage definitions a. the input pulse is supplied by a generator having the following characteristics: prr 125 khz, 50% duty cycle, t r 6 ns, t f 6 ns, z o = 50 ? . figure 17. driver test circuit and voltage waveforms figure 18. receiver voltage and current definitions 0 or vcc 1 v i txd canh canl v o(canl ) v o(canh) v od i o(canh) i o(canl ) gnd2 gnd1 gnd1 gnd2 i i v oc v o(canh) + v o(canl ) 2 r l v i (see note a) v o txd canl canh c vcc /2 vcc /2 vcc t f t r t plh t phl 10% 90% 0.9v 0 v v o(d) v o(r) 0.5v v i v o r l l ? 2. 5 v ? 3 . 5 v ? 1. 5 v recessive dominant o (canh) v o (canl) v rxd canh canl gnd2 gnd1 v i(canh) v i(canl) i o v ic v i(canh) = v i(canl) + 2 v id v o
16 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated test circuits (continued) a. the input pulse is supplied by a generator having the following characteristics: prr 125 khz, 50% duty cycle, t r 6 ns, t f 6 ns, z o = 50 ? . figure 19. receiver test circuit and voltage waveforms table 1. receiver differential input voltage threshold test input output v canh v canl |v id | rxd -29.5 v -30.5 v 1000 mv l v ol 30.5 v 29.5 v 1000 mv l -19.55 v -20.45 v 900 mv l 20.45 v 19.55 v 900 mv l -19.75 v -20.25 v 500 mv h v oh 20.25 v 19.75 v 500 mv h -29.8 v -30.2 v 400 mv h 30.2 v 29.8 v 400 mv h open open x h figure 20. t loop test circuit and voltage waveforms rxd canh canl gnd 2 gnd 1 v i (see note a ) 1 .5 v i o v o v i v o 2 v 2.4 v 3.5 v v oh t f t r t phl 1.5 v v ol 90 % 10 % 0.3 vcc 1 0.7 vcc 1 t plh c l(rxd) txd rxd v i canh canl + v o _ gnd1 txd input 0 v vcc output rxd 50% 50% v oh v ol t loop 1 50% t loop2 r l c l c l(rxd)
17 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated figure 21. can fd timing parameter measurement a. the input pulse is supplied by a generator having the following characteristics: t r 6 ns, t f 6 ns, z o = 50 ? . figure 22. dominant time-out test circuit and voltage waveforms figure 23. driver short-circuit current test circuit and waveforms canh canh txd (see note a ) c l v i v od gnd 1 vcc v i v od 500 mv 900 mv 0 v v od (d) 0 v t txd_dto r l r l canh canl txd c l v o c l(rxd) rxd v i txd v diff 70% 500 mv 30% 30% 900 mv v i 0v t bit(bus) rxd v oh v ol 70% 30% t bit(rxd) t bit(txd) gnd1 5 x t bit canh canl txd 0v v bus v bus i os v bus 0v v bus v bus or i os gnd2 200 s +
18 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated figure 24. common-mode transient immunity test circuit v ol v oh or txd rxd v cc 1 1 k w 60 w v cc2 gnd 1 v cm gnd 2 c l = 15 pf (includes probe and jig capacitance ) c = 0.1 f 1% m canh canl gnd1 c = 0.1 f m 1% s 1 0 v v ol v oh or gnd 2 v cc 1 +
19 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the iso1042 device is a digitally isolated can transceiver that offers 70-v dc bus fault protection and 30-v common-mode voltage range. the device supports up to 5-mbps data rate in can fd mode allowing much faster transfer of payload compared to classic can. the iso1042 device has an isolation withstand voltage of 5000 v rms and is available in basic and reinforced isolation with a surge test voltage of 6 kv pk and 10 kv pk respectively. the device can operate from 1.8-v, 2.5-v, 3.3-v, and 5-v supplies on side 1 and a 5-v supply on side 2. this supply range is of particular advantage for applications operating in harsh industrial environments because the low voltage on side 1 enables the connection to low-voltage microcontrollers for power conservation, whereas the 5 v on side 2 maintains a high signal-to-noise ratio of the bus signals. 8.2 functional block diagram 8.3 feature description 8.3.1 can bus states the can bus has two states during operation: dominant and recessive . a dominant bus state, equivalent to logic low, is when the bus is driven differentially by a driver. a recessive bus state is when the bus is biased to a common mode of v cc / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic high. the host microprocessor of the can node uses the txd pin to drive the bus and receives data from the bus on the rxd pin. see figure 25 and figure 26 . + rxd txd v cc1 gnd1 v cc2 gnd2 canh canl galvanic isolation copyright ? 2017, texas instruments incorporated
20 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated feature description (continued) figure 25. bus states (physical bit representation) figure 26. simplified recessive common mode bias and receiver 8.3.2 digital inputs and outputs: txd (input) and rxd (output) the v cc1 supply for the isolated digital input and output side of the device can be supplied by 1.8-v, 2.5-v, 3.3-v, and 5-v supplies and therefore the digital inputs and outputs are 1.8-v, 2.5-v, 3.3-v, and 5-v compatible. note the txd pin is very weakly internally pulled up to v cc1 . an external pullup resistor should be used to make sure that the txd pin is biased to recessive (high) level to avoid issues on the bus if the microprocessor does not control the pin and the txd pin floats. the txd pullup strength and can bit timing require special consideration when the device is used with an open-drain txd output on the can controller of the microprocessor. an adequate external pullup resistor must be used to make sure that the txd output of the microprocessor maintains adequate bit timing input to the input on the transceiver. rxd v cc / 2 canh canl galvanic isolation 43 2 1 typical bus voltage (v) normal and silent mode time (t) recessive logic h dominant logic l recessive logic h canh canl v diff(d) v diff(r)
21 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated feature description (continued) 8.3.3 protection features 8.3.3.1 txd dominant timeout (dto) the txd dto circuit prevents the transceiver from blocking network communication in the event of a hardware or software failure where the txd pin is held dominant longer than the timeout period, t txd_dto . the dto circuit timer starts on a falling edge on the txd pin. the dto circuit disables the can bus driver if no rising edge occurs before the timeout period expires, which frees the bus for communication between other nodes on the network. the can driver is activated again when a recessive signal occurs on the txd pin, clearing the txd dto condition. the receiver and rxd pin still reflect activity on the can bus, and the bus terminals are biased to the recessive level during a txd dominant timeout. figure 27. example timing diagram for txd dto note the minimum dominant txd time (t txd_dto ) allowed by the txd dto circuit limits the minimum possible transmitted data rate of the device. the can protocol allows a maximum of eleven successive dominant bits (on txd) for the worst case, where five successive dominant bits are followed immediately by an error frame. this, along with the t txd_dto minimum, limits the minimum data rate. calculate the minimum transmitted data rate with equation 1 . minimum data rate = 11 / t txd_dto (1) 8.3.3.2 thermal shutdown (tsd) if the junction temperature of the device exceeds the thermal shutdown threshold (t tsd ), the device turns off the can driver circuits, blocking the txd-to-bus transmission path. the can bus terminals are biased to the recessive level during a thermal shutdown, and the receiver-to-rxd path remains operational. the shutdown condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature (t tsd_hyst ) below the thermal shutdown temperature (t tsd ) of the device. rxd (receiver) txd (driver) can bus signal normal can communication txd fault stuck dominant example: pcb failure or bad software driver disabled freeing bus for other nodes bus would be stuck dominant , blocking communication for the whole network but txd dto prevents this and frees the bus for communication after the t txd_dto time. t txd_dto t txd_dto fault is repaired and transmission capability is restored communication from other bus nodes communication from repaired nodes communication from other bus nodes communication from repaired nodes communication from local node
22 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated feature description (continued) 8.3.3.3 undervoltage lockout and default state the supply pins have undervoltage detection that places the device in protected or default mode which protects the bus during an undervoltage event on the v cc1 or v cc2 supply pins. if the bus-side power supply, v cc2 , is less than about 4 v, the power shutdown circuits in the iso1042 device disable the transceiver to prevent false transmissions because of an unstable supply. if the v cc1 supply is still active when this occurs, the receiver output (rxd) goes to a default high (recessive) value. table 2 summarizes the undervoltage lockout and fail- safe behavior. table 2. undervoltage lockout and default state v cc1 v cc2 device state bus output rxd > uv vcc1 > uv vcc2 functional per device state and txd mirrors bus < uv vcc1 > uv vcc2 protected recessive undetermined > uv vcc1 < uv vcc2 protected high impedance recessive (default high) note after an undervoltage condition is cleared and the supplies have returned to valid levels, the device typically resumes normal operation in 300 s. 8.3.3.4 floating pins pullup and pulldown resistors should be used on critical pins to place the device into known states if the pins float. the txd pin should be pulled up through a resistor to the v cc1 pin to force a recessive input level if the microprocessor output to the pin floats. 8.3.3.5 unpowered device the device is designed to be ideal passive or no load to the can bus if it is unpowered. the bus pins (canh, canl) have extremely low leakage currents when the device is unpowered to avoid loading down the bus which is critical if some nodes of the network are unpowered while the rest of the of network remains in operation. 8.3.3.6 can bus short circuit current limiting the device has two protection features that limit the short circuit current when a can bus line has a short-circuit fault condition. the first protection feature is driver current limiting (both dominant and recessive states) and the second feature is txd dominant state time out to prevent permanent higher short circuit current of the dominant state during a system fault. during can communication the bus switches between dominant and recessive states, therefore the short circuit current may be viewed either as the instantaneous current during each bus state or as an average current of the two states. for system current (power supply) and power considerations in the termination resistors and common-mode choke ratings, use the average short circuit current. determine the ratio of dominant and recessive bits by the data in the can frame plus the following factors of the protocol and phy that force either recessive or dominant at certain times: ? control fields with set bits ? bit stuffing ? interframe space ? txd dominant time out (fault case limiting) these factors ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage of dominant bits. the short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short circuit currents. use equation 2 to calculate the average short circuit current. i os(avg) = %transmit [(%rec_bits i os(ss)_rec ) + (%dom_bits i os(ss)_dom )] + [%receive i os(ss)_rec ] where ? i os(avg) is the average short circuit current ? %transmit is the percentage the node is transmitting can messages ? %receive is the percentage the node is receiving can messages
23 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated ? %rec_bits is the percentage of recessive bits in the transmitted can messages ? %dom_bits is the percentage of dominant bits in the transmitted can messages ? i os(ss)_rec is the recessive steady state short circuit current ? i os(ss)_dom is the dominant steady state short circuit current (2) note consider the short circuit current and possible fault cases of the network when sizing the power ratings of the termination resistance and other network components. 8.4 device functional modes table 3 and table 4 list the driver and receiver functions. table 5 lists the functional modes for the iso1042 device. (1) h = high level, l = low level, z = common mode (recessive) bias to v cc / 2. see figure 25 and figure 26 for bus state and common mode bias information. table 3. driver function table input outputs driven bus state txd (1) canh (1) canl (1) l h l dominant h z z recessive (1) see receiver electrical characteristics section for input thresholds. (2) h = high level, l = low level, ? = indeterminate. table 4. receiver function table device mode can differential inputs v id = v canh ? v canl (1) bus state rxd pin (2) normal v id v it(max) dominant l v it(min) < v id < v it(max) ? ? v id v it(min) recessive h open (v id 0 v) open h (1) h = high level; l = low level; x = irrelevant; ? = indeterminate; z = high impedance (2) see receiver electrical characteristics section for input thresholds. (3) logic low pulses to prevent dominant time-out. table 5. function table (1) driver receiver inputs outputs bus state differential inputs v id = canh ? canl (2) output rxd bus state txd canh canl l (3) h l dominant v id v it(max) l dominant h z z recessive v it(min) < v id < v it(max) ? ? open z z recessive v id v it(min) h recessive x z z recessive open (v id 0 v) h recessive
24 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the iso1042 device can be used with other components from texas instruments such as a microcontroller, a transformer driver, and a linear voltage regulator to form a fully isolated can interface. 9.2 typical application figure 28. application circuit with iso1042 in 16-soic package psu tps76350 12 4 35 6 7 8 14 13 12 9,10,15 in en gnd nc out 13 54 2 txd v cc1 rxd nc nc gnd1 gnd1 nc nc canh gnd2 43 2 6 5 1 canl 7 8 11,16 v cc2 mcu rxd txd v dd dgnd l1 n pe 3.3v 0v protective earth chasis ground digital ground iso ground optional bus protection function galvanic isolation barrier sn6505 v cc d2 d1 gnd clk en 3.3 v iso1042 gnd1 v cc1 txd nc rxd nc nc gnd1 gnd2 canh nc
25 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical application (continued) figure 29. application circuit with iso1042 in 8-soic package 9.2.1 design requirements unlike an optocoupler-based solution, which requires several external components to improve performance, provide bias, or limit current, the iso1042 device only requires external bypass capacitors to operate. 9.2.2 detailed design procedure 9.2.2.1 bus loading, length and number of nodes the iso 11898-2 standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m. however, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. a large number of nodes requires transceivers with high input impedance such as the iso1042 transceivers. many can organizations and standards have scaled the use of can for applications outside the original iso 11898-2 standard. these organizations and standards have made system-level trade-offs for data rate, cable length, and parasitic loading of the bus. examples of some of these specifications are arinc825, canopen, devicenet, and nmea2000. the iso1042 device is specified to meet the 1.5-v requirement with a 50- ? load, incorporating the worst case including parallel transceivers. the differential input resistance of the iso1042 device is a minimum of 30 k ? . if 100 iso1042 transceivers are in parallel on a bus, this requirement is equivalent to a 300- ? differential load worst case. that transceiver load of 300 ? in parallel with the 60 ? gives an equivalent loading of 50 ? . therefore, the iso1042 device theoretically supports up to 100 transceivers on a single bus segment. however, for can network design margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances, ground offsets and signal integrity, therefore a practical maximum number of nodes is typically much lower. bus length may also be extended beyond the original iso 11898 standard of 40 m by careful system design and data-rate tradeoffs. for example, canopen network design guidelines allow the network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes, and a significantly lowered data rate. this flexibility in can network design is one of the key strengths of the various extensions and additional standards that have been built on the original iso 11898-2 can standard. using this flexibility requires the responsibility of good network design and balancing these tradeoffs. tps76350 12 4 3 76 5 in en gnd nc out 13 54 2 txd v cc1 rxd gnd1 canh 43 2 6 5 1 canl 7 8 8 v cc2 mcu rxd txd v dd dgnd digital ground iso ground sn6505 optional bus protection function v cc d2 d1 gnd clk galvanic isolation barrier iso1042 en 3.3 v gnd2 3.3 v copyright ? 2017, texas instruments incorporated
26 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical application (continued) 9.2.2.2 can termination the iso11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with 120- characteristic impedance (z o ). resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to prevent signal reflections. unterminated drop-lines (stubs) connecting nodes to the bus should be kept as short as possible to minimize signal reflections. the termination may be in a node, but if nodes are removed from the bus, the termination must be carefully placed so that it is not removed from the bus. figure 30. typical can bus termination may be a single 120- resistor at the end of the bus, either on the cable or in a terminating node. if filtering and stabilization of the common-mode voltage of the bus is desired, then split termination can be used. (see figure 31 ). split termination improves the electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions. figure 31. can bus termination concepts node 1 can transceiver mcu or dsp can controller node 2 can transceiver mcu or dsp can controller node 3 can transceiver mcu or dsp can controller node n (with termination) can transceiver mcu or dsp can controller r term r term can transceiver can transceiver canh canl canh canl r term r term / 2 r term / 2 c split standard termination split termination
27 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical application (continued) 9.2.3 application curve figure 32. typical txd, rxd, canh and canl waveforms at 1 mbps 9.3 devicenet application figure 33. iso1042, iso1211 and sn6505 used in a devicenet application v cc1 out gnd1 fgnd in sense 560 ldo v out v in gnd 5 6 7 8 v cc2 canh canl gnd2 tps7b82-q1 v cc1 txd rxd gnd1 mcu vdd vcc1 ldo v in gnd v out v cc1 sn6505 v cc d2 d1 gnd clk en 1 : 4 24 v v cc2 = 5v bss123 bss123 12 3 4 iso ground 24 v sense v cc1 txd rxd dgnd 2.25 k v cc1 iso ground 24 v canh canl 24ret iso1211d iso1042 v cc2 = 5 v digital ground
28 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated devicenet application (continued) figure 33 shows an application circuit for using iso1042, iso1211 and sn6505 in a devicenet application. iso1042 is used to isolate the can interface. the iso1211 24-v digital input receiver is used to detect the absence or presence of the 24-v field supply. the sn6505 push-pull transformer driver, is used to create an auxiliary isolated power supply for the micro-controller side using the 24-v field supply. 10 power supply recommendations to make sure operation is reliable at all data rates and supply voltages, a 0.1- f bypass capacitor is recommended at the input and output supply pins (v cc1 and v cc2 ). the capacitors should be placed as close to the supply pins as possible. in addition, a bulk capacitance, typically 4.7 f, should be placed near the v cc2 supply pin. if only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as ti's sn6505b . for such applications, detailed power supply design, and transformer selection recommendations are available in the sn6505 low-noise 1-a transformer drivers for isolated power supplies data sheet .
29 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 11 layout 11.1 layout guidelines a minimum of four layers is required to accomplish a low emi pcb design (see figure 34 ). layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. ? routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. ? placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. ? placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pf/in 2 . ? routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. suggested placement and routing of iso1042 bypass capacitors and optional tvs diodes is shown in figure 35 and figure 36 . in particular, place the v cc2 bypass capacitors on the top layer, as close to the device pins as possible, and complete the connection to the v cc2 and g nd2 pins without using vias. note that the soic-16 variant needs two v cc2 bypass capacitor, one on each v cc2 pin. if an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. this makes the stack mechanically stable and prevents it from warping. also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. for detailed layout recommendations, refer to the digital isolator design guide . 11.1.1 pcb material for digital circuit boards operating at less than 150 mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard fr-4 ul94v-0 printed circuit board. this pcb is preferred over lower- cost alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics. 11.2 layout example figure 34. recommended layer stack 10 mils 10 mils 40 mils fr-4 0 r ~ 4.5 keep this space free from planes, traces, pads, and vias ground plane power plane low-speed traces high-speed traces
30 iso1042 sllsf09c ? december 2017 ? revised september 2018 www.ti.com product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated layout example (continued) figure 35. 16-dw layout example figure 36. 8-dwv layout example v cc1 txd rxd gnd1 v cc2 canh canl gnd2 gnd1 plane gnd2 plane c v cc1 v cc2 minimize distance to v cc c c2 d1 c1 isolation capacitor mcu can bus gnd1 plane minimize distance to v cc x x x gnd1 v cc1 txd nc rxd gnd1 nc nc isolation capacitor v cc2 gnd2 nc canh canl v cc2 gnd2 gnd2 c 0.1 f v cc1 c 0.1 f v cc2 gnd1 plane gnd2 plane d1 c2 c1 can bus mcu c 0.1 f
31 iso1042 www.ti.com sllsf09c ? december 2017 ? revised september 2018 product folder links: iso1042 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? texas instruments, digital isolator design guide ? texas instruments, iso1042dw isolated can transceiver evaluation module user ' s guide ? texas instruments, isolate your can systems without compromising on performance or space ti technote ? texas instruments, isolation glossary ? texas instruments, high-voltage reinforced isolation: definitions and test methodologies ? texas instruments, how to isolate signal and power in isolated can systems ti technote 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resource the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 29-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ISO1042BDW active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 iso1042b ISO1042BDWr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 iso1042b ISO1042BDWv preview soic dwv 8 64 tbd call ti call ti -40 to 125 ISO1042BDWvr preview soic dwv 8 1000 tbd call ti call ti -40 to 125 iso1042dw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 iso1042 iso1042dwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 iso1042 iso1042dwv preview soic dwv 8 40 tbd call ti call ti -40 to 125 iso1042dwvr preview soic dwv 8 1000 tbd call ti call ti -40 to 125 xiso1042dwr active soic dw 16 2000 tbd call ti call ti -40 to 125 xiso1042dwvr active soic dwv 8 1000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
package option addendum www.ti.com 29-sep-2018 addendum-page 2 (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
www.ti.com package outline c typ 11.5 0.25 2.8 max typ 0.33 0.13 0 -8 6x 1.27 8x 0.51 0.31 2x 3.81 0.46 0.36 1.0 0.5 0.25 gage plane a note 3 5.95 5.75 b note 4 7.6 7.4 (2.286) (2) 4218796/a 09/2013 soic - 2.8 mm max height dwv0008a soic notes: 1. all linear dimensions are in millimeters. dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm, per side. 1 8 0.25 c a b 5 4 area pin 1 id seating plane 0.1 c see detail a detail a typical scale 2.000
www.ti.com example board layout (10.9) 0.07 max all around 0.07 min all around 8x (1.8) 8x (0.6) 6x (1.27) 4218796/a 09/2013 soic - 2.8 mm max height dwv0008a soic symm symm see details land pattern example 9.1 mm nominal clearance/creepage scale:6x notes: (continued) 5. publication ipc-7351 may have alternate designs. 6. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder mask opening non solder mask defined solder mask details opening solder mask metal solder mask defined
www.ti.com example stencil design 8x (1.8) 8x (0.6) 6x (1.27) (10.9) 4218796/a 09/2013 soic - 2.8 mm max height dwv0008a soic notes: (continued) 7. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 8. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:6x symm symm
generic package view images above are just a representation of the package family, actual package may vary. refer to the product data sheet for package details. dw 16 soic - 2.65 mm max height small outline integrated circuit 4040000-2/h
www.ti.com package outline c typ 10.63 9.97 2.65 max 14x 1.27 16x 0.51 0.31 2x 8.89 typ 0.33 0.10 0 - 8 0.3 0.1 (1.4) 0.25 gage plane 1.27 0.40 a note 3 10.5 10.1 b note 4 7.6 7.4 4221009/b 07/2016 soic - 2.65 mm max height dw0016b soic notes: 1. all linear dimensions are in millimeters. dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm, per side. 5. reference jedec registration ms-013. 1 16 0.25 c a b 9 8 pin 1 id area seating plane 0.1 c see detail a detail a typical scale 1.500
www.ti.com example board layout (9.75) r0.05 typ 0.07 max all around 0.07 min all around (9.3) 14x (1.27) r0.05 typ 16x (1.65) 16x (0.6) 14x (1.27) 16x (2) 16x (0.6) 4221009/b 07/2016 soic - 2.65 mm max height dw0016b soic symm symm see details 1 8 9 16 symm hv / isolation option 8.1 mm clearance/creepage notes: (continued) 6. publication ipc-7351 may have alternate designs. 7. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder mask opening non solder mask defined solder mask details opening solder mask metal solder mask defined land pattern example scale:4x symm 1 8 9 16 ipc-7351 nominal 7.3 mm clearance/creepage see details
www.ti.com example stencil design r0.05 typ r0.05 typ 16x (1.65) 16x (0.6) 14x (1.27) (9.75) 16x (2) 16x (0.6) 14x (1.27) (9.3) 4221009/b 07/2016 soic - 2.65 mm max height dw0016b soic notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. symm symm 1 8 9 16 hv / isolation option 8.1 mm clearance/creepage solder paste example based on 0.125 mm thick stencil scale:4x symm symm 1 8 9 16 ipc-7351 nominal 7.3 mm clearance/creepage
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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